This invention relates to clock generator circuits as used in semiconductor memory devices, and more particularly to delay circuits of the type employed in dynamic read/write memory devices.
Dynamic read/write memory devices are generally constructed as illustrated in U.S. Pat. No. 4,071,801 issued to White, McAdams, and Redwine (a 16K-bit device) and U.S. Pat. No. 4,293,993 issued to McAlexander, White and Rao (a 64K-bit device), both patents assigned to Texas Instruments. In such devices, a clock voltage is needed at a number of delay times. The circuits ordinarily used to generate these delayed clocks are of the type disclosed in U.S. Pat. No. 4,239,991, issued to Ngai H. Hong et al, assigned to Texas Instruments. Although, various methods have been employed to reduce the power dissipation in these clock delay circuits, the excess current is still a problem especially for high density devices of the 256K-bit and 1-Mbit size and also the physical size of the circuits and the output voltage characteristics have been unsatisfactory.
It is the principal object of this invention to provide improved, low-power, clock delay circuitry for dynamic read/write memory devices or the like. Another object is to avoid the excess sizes, and undesired output voltage characteristics of clock delay circuits.